Current Testing for CMOS Static RAMs to Reduce Testing Costs.

Testing for parametric faults in static CMOS circuits

Many defects causing bridges, breaks, and transistor stuck-ons in static CMOS circuits are not detected by tests generated using the traditional single stuck-at fault model. These undetected, non-traditional faults may be detected as increased propagation time or as excessive quiescent power supply current (I DDQ). In this paper we compare the cost of testing for excess I DDQ caused by bridge, ...

Quiescent Current Testing of Cmos Data Converters

ii ACKNOWLEDGMENTS I dedicate my work to my parents Mr. Nageswara Rao and Mrs. Vijaya Lakshmi, my brother and sister-in law Mr. Sapta Nag and Mrs. Parimala and my grandparents Mr. Gandhi and Mrs. Sambrajam for their constant support and encouragement throughout my life. I am very grateful to my advisor Dr. A. Srivastava for his guidance, patience and understanding throughout this work. His sugg...

Toxicity Testing and the Toxicity Testing and the Current Situation in IRAN

Toxicity Testing and the Toxicity Testing and the Current Situation in IRAN

Testing for Bounded Faults in RAMs

We study the class of “bounded faults” in random-access memories; these are faults that involve a bounded number of cells. This is a very general class of memory faults that includes, for example, the usual stuck-at, coupling, and pattern-sensitive faults, but also many other types of faults. Some bounded faults are known to require deterministic tests of length proportional to n log2 n, where ...